Andes Firmware Image layout as seen in MT76 Wifi Chipsets: GraphViz block diagram (.dot) source

Firmware image found with MediaTek MT76xx wifi chipsets.

Application

Firmware Image wifi chipset

KS implementation details

License: CC0-1.0

This page hosts a formal specification of Andes Firmware Image layout as seen in MT76 Wifi Chipsets using Kaitai Struct. This specification can be automatically translated into a variety of programming languages to get a parsing library.

GraphViz block diagram source

andes_firmware.dot

digraph {
	rankdir=LR;
	node [shape=plaintext];
	subgraph cluster__andes_firmware {
		label="AndesFirmware";
		graph[style=dotted];

		andes_firmware__seq [label=<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0">
			<TR><TD BGCOLOR="#E0FFE0">pos</TD><TD BGCOLOR="#E0FFE0">size</TD><TD BGCOLOR="#E0FFE0">type</TD><TD BGCOLOR="#E0FFE0">id</TD></TR>
			<TR><TD PORT="image_header_pos">0</TD><TD PORT="image_header_size">32</TD><TD>ImageHeader</TD><TD PORT="image_header_type">image_header</TD></TR>
			<TR><TD PORT="ilm_pos">32</TD><TD PORT="ilm_size">image_header.ilm_len</TD><TD></TD><TD PORT="ilm_type">ilm</TD></TR>
			<TR><TD PORT="dlm_pos">...</TD><TD PORT="dlm_size">image_header.dlm_len</TD><TD></TD><TD PORT="dlm_type">dlm</TD></TR>
		</TABLE>>];
		subgraph cluster__image_header {
			label="AndesFirmware::ImageHeader";
			graph[style=dotted];

			image_header__seq [label=<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0">
				<TR><TD BGCOLOR="#E0FFE0">pos</TD><TD BGCOLOR="#E0FFE0">size</TD><TD BGCOLOR="#E0FFE0">type</TD><TD BGCOLOR="#E0FFE0">id</TD></TR>
				<TR><TD PORT="ilm_len_pos">0</TD><TD PORT="ilm_len_size">4</TD><TD>u4le</TD><TD PORT="ilm_len_type">ilm_len</TD></TR>
				<TR><TD PORT="dlm_len_pos">4</TD><TD PORT="dlm_len_size">4</TD><TD>u4le</TD><TD PORT="dlm_len_type">dlm_len</TD></TR>
				<TR><TD PORT="fw_ver_pos">8</TD><TD PORT="fw_ver_size">2</TD><TD>u2le</TD><TD PORT="fw_ver_type">fw_ver</TD></TR>
				<TR><TD PORT="build_ver_pos">10</TD><TD PORT="build_ver_size">2</TD><TD>u2le</TD><TD PORT="build_ver_type">build_ver</TD></TR>
				<TR><TD PORT="extra_pos">12</TD><TD PORT="extra_size">4</TD><TD>u4le</TD><TD PORT="extra_type">extra</TD></TR>
				<TR><TD PORT="build_time_pos">16</TD><TD PORT="build_time_size">16</TD><TD>str(UTF-8)</TD><TD PORT="build_time_type">build_time</TD></TR>
			</TABLE>>];
		}
	}
	andes_firmware__seq:image_header_type -> image_header__seq [style=bold];
	image_header__seq:ilm_len_type -> andes_firmware__seq:ilm_size [color="#404040"];
	image_header__seq:dlm_len_type -> andes_firmware__seq:dlm_size [color="#404040"];
}